A High-Throughput Cost-Effective ASIC Implementation of the AES Algorithm

摘要：

This paper proposes a high-throughput cost effective implementation of AES supporting encryption and decryption with 128-,192-,and 256-bit cipher key. Optimum irreducible polynomial coefficients are selected to construct the composite field GF(((22)2)2)on standard and normal base in order to minimize the gate count in subBytes/Inv Sub Bytes transformation.In addition,Mix Coulmn/Inv Mix Column transformations are optimized and the gate count is the least as we know. And then,a novel on-the-fly key expansion structure is applied to improve the throughput. The performance is evaluated on SMIC 0.18μm CMOS technology and the design has been verified on FPGA. The throughput can achieve at 1.16Gbps with the cost of only 19476 equivalent NAND2 gates,which outperforms prior works with respect to the parameter throughput per kilo gates with the same process.

关键词： composite field irreducible polynomial coefficients standard and normal base on-the-fly key ezpansion

作者: Qingfu Cao Shuguo Li

作者单位: Institute of Microelectronics,Tsinghua University,Beijing,China Institute of Mieroelectronics,Tsinghua University,Beijing,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 805-808

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）