A Fast-lock Digital Delay-Locked Loop Controller

摘要：

A fast-lock digital delay-locked loop(DLL) is presented in this paper. A delay compensation circuit (DCC) is used to achieve short lock time. The DLLs initial value is controlled by the DCC,so that initial delay time of the delay line can be located in the expected scope and there is only one stable state in various process, voltage,and temperature (PVT) conditions.Since the delay time of each delay cell changes based on the variations of PVT conditions,the output values generated by the DCC are determinate of the PVT conditions in the chip. Thus the DLLs initial state changes according to the detected PVT conditions,and the initial large phase difference is eliminated by the DCC.So it can be fast locked and only has one stable state. The proposed digital DLL overcomes the drawbacks of traditional DLL which may have more than one stable state. The HSPICE simulation results show that the proposed digital DLL circuit achieves fine accuracy and the maximum lock time is 16 clock cycles.

关键词： Delay-locked loops (DLL) delay compensa-tion circuit(DCC) PVT

作者: Bo Ye Tianwang Li Xingcheng Han Min Luo

作者单位: Institute of Microelectronics,Shanghai University of Electric Power,Shanghai,200090,China Department of Integrated Circuit & Commumcation Software,Wuhan University,Wuhan,430079,China Integrated Silicon Solution(Shanghai) Co.,Ltd,Shanghai,201203,China Lucent Technologies Optical Networks Co.,Ltd.,Shanghai,200233,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 809-812

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）