Performance Evaluation of the Memory Hierarchy Design on CMP Prototype Using FPGA

摘要：

The importance of the memory hierarchy has increased with advances in performance of processors in Chip Multi-Processor(CMP)system.However,the research of on chip memory subsystem for Multiprocessor has not been undertaken thoroughly.In this paper,we develop two distributed shared memory hierarchies based on distributed shared-bus and Network-on-Chip(NoC),and the performances of these prototype designs are evaluated under JPEG decoding application,and implement them on a FPGA device.We compare the performance between the different on chip memory subsystem with the application,and the results show that the distributed shared memory hierarchy based on distributed shared-bus provides the best performance of speedup ratio with the least processor and that the NoC memory hierarchy provides the best performance of speedup ratio with the more processors.

关键词： Memory Hierarchy Shared-Bus Network-on-Chip(NoC) Evaluate

作者: Liu Yan Li Dongsheng Zhang Duoli Du Gaoming Wang Jian Gao Minglun Wen Haihua Geng Luofeng

作者单位: VLSI Research Institute,Hefei University of Technology,Hefei,China East China Institute of Photo-Ele VLSI Research Institute,Hefei University of Technology,Hefei,China East China Institute of Photo-Electronic,Benghu,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 813-816

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）