Power-Aware FPGA Packing Algorithm

摘要：

Field-Programmable Gate Array (FPGA) packing is one of abstraction levels in the FPGA CAD design flow which is aimed to pack logic components into clusters. As a result,the cluster-based FPGA can significantly improve timing,routability and power consumption as well. This paper proposes a novel packing algorithm using priori wire length estimation before actual routing taken apart.In addition, global placement was taken apart before packing to have additional placement information,which is also guided for the algorithm to selectively pack closely related module into one cluster.Experimental results show that power-aware packing algorithm achieves 5% power reduction on average compared to traditional algorithm.

关键词： FPGA Power dissipation EDA Algorithm

作者: M.Yang Hongying Xu A.E.A.Almaini

作者单位: State Key Lab of ASIC & System,Department of Microelectronics,Fudan University,China Tianjin Vocational College of Mechanics and Electricity,Tianjin,300131,China School of Engineering,Napier University,Edinburgh,UK

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 817-819

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）