High Computing-Intensive Array System Design and Hardware Implement
This paper addresses a novel coarse grain dynamic reconfigurable computing system,called DReAC-2, design and hardware implement. A whole DReAC-2 system integrates a Nios Ⅱ processor,which manages the whole reconfigurable system,and a dynamic reconfigurable coprocessor,which comprises of an 8x8 processing node array designed for high regularity,high computation intensive tasks.Hardware prototype of DReAC-2 has been implemented on the ALTERA STRATIX Ⅱ EP2S180 development board. According to tasks nature,MIMd computing array can select either parallel-pipelined pattern or array-parallel pattern to gain the better performance. The experiment results show that DReAC-2 achieves much higher 10～100x factor than NIOS Ⅱ processors,and 2x～4x factors and higher precision than some others reconfigurable processors.
Reconfigurable Computing System High Computation-intensive Array-Parallel Parallel-Pipeline
Yu-kun Song Xiao-lei Wang Wei Ni Duo-li Zhang Gao-ming Du
Institute of VLSI Design,Hefei University of Technology,Hefei 230009,China
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
820-823
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）