A Power and Area Efficient Architecture of Convolver Based on Ram
This paper proposes a novel architecture of the cortvolver which can also be used as a correlator (depend on the order in which the input sequence are put in).it is power and area efficient compared with the typical architectures based on registers. Two groups of convolver are implemented to show the improvement. One group deals with two 12bit data sequences of length 64,while another deals with two 12bit data sequences of length 256,with each group containing a ram based one and a conventional one. The synthesis results by DC using SMIC 0.13um library and the results of Prime Power shows that in the second group,the area and power of the ram based one can be reduced to 91% and only 77% of the conventional one,respectively.
Convolver correlator ram register power area
Chen Chen Yun Chen Yuan Chen An Pan Xiao-Yang Zeng
State Key Lab of ASIC & System,Fudan University,Shanghai 201203,P.R.China
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
835-838
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）