A Design of Level Interface for CMP based Cache System

摘要：

This paper proposes a level interface for two-level Cache sub-system based on a 4-core CMP system. This interface module successfully connects L1-Cache and L2 Cache.Several optimizations are utilized in the design,which contribute to the realization of high-efficient communication between the two levels,lowering L1-Cache miss penalty,and the improvement of processing efficiency of access requests.

关键词： Pipeline Cache Multi-port Miss Penalty

作者: Chen Chen Hu He Yuan Liu

作者单位: Institute of Mieroelectronics,Tsinghua University,Tsinghna National Laboratory of Information and Te Institute of Microelectronics,Tsinghua University

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 839-842

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）