Scalable and Unified Hardware Architecture for Montgomery Inversion Computation in GF(p) and GF(2n)

摘要：

Computing the inverse of a number in finite fields GF(p) or GF(2n) is equally important for cryptographiC applications.In this paper four optimized Montgomery inverse algorithms are proposed to achieve high speed and flexibility. Then a novel scalable and unified architecture for Montgomery inverse hardware that operates in both GF(p) and GF(2n)is proposed. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate with better or similar speed, and it takes less number of clock cycle as the datapath of scalable design is large and can also achieve high clock frequency.Finally this work has been verified by modeling it in Verilog-HDL,implementing it under 0.18μm SMIC technology. The result indicates that our work has advanced performance than other works.

关键词： Montgomery Inversion GF(p) GF(2n) Unified architecture

作者: Yang Xiao-hui Qin Fan Dai Zi-bin Zhang yong-fu

作者单位: Institute of Electronic Technology,Information Engineering University,Zhengzhou,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 843-846

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）