Design and Optimization on Reconfigurable Butterfly Core for a Real-Time FFT Processor

摘要：

Runtime reconfigurable FFT processors on scale of data frame samples are being concerned and designed. A novel solution based on the reusable butterfly core is proposed for achievement of reconfigurable FFT processors. An alternative mixed fabric in radix-4 and radix-2 is applied to the proposed butterfly core.Parallel in-place memory access rule is proposed to fulfill the range of data frame sample scale,from 1024 to 16,with the recursive architecture of the single butterfly core.Implementation of the proposed FFT processor is under the technology of SMIC 0.18μm CMOS,which gets to 3 ns on critical path and 2 mm2 of a core area by reason of the optimization solution on data paths with 4-2 compressor clusters,instead of regular adders,and on data A,which is the data without rotation in the dragonfly core,with preprocessing.

关键词： Runtime Configurable FFT Reconfigurable Butterfly Core Radiz-4 Radiz-2

作者: Zhizhe Liu Shunan Zhong Yueyang Chen Weinan Chu

作者单位: Beijing Institute of Technology,Beijing,BJ 100081 CHINA Electrical Engineering Department,Beijing Institute of Technology,Beijing,BJ 100081 CHINA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 847-850

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）