A Parallel Intra Prediction Architecture for H.264 Video Decoding

摘要：

In this paper,an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations.Compared with conventional architecture,intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx H FPGA.

关键词： H.264 intra prediction decoding hardware

作者: Xi WANG Xiaoxin CUI Dunshan YU

作者单位: Institute of Microelectronics,Peking University,Beijing 100871,P.R.China Institute of Microelectronics,Peking University,Beijing 100871.P.R.China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 859-862

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）