A 1Gsample/Sec Non-Recursive Sharpened Cascaded Integrator-Comb Filter with 70 dB alias rejection and 0.003 dB droop in 0.18-μm CMOS

摘要：

A new architecture for the implementation of very high speed digital decimation filters is de-scribed.It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filters passband response. A SPT-encoded non-recursive technique is further applied to realize parallel computation and improve the maximum clock rate of the filter.With a 0.18-μm CMOS process,the filter can achieve a greater than 1 GHz clock rate even as we trade off speed for power consumption and area. The maximum achievable clock rate exceeds 2.5 GHz in 0.18-μm CMOS.Such high speed capability enables it to be employed in wide-band communication systems such as 3G cellular applications.

关键词： CIC Digital Filter CMOS Multirate

作者: Xiong Liu Alan N.Willson,Jr

作者单位: Electrical Engineering Department,University of Califorma,Los Angeles,CA 90095 USA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 867-870

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）