Single-Phase Adiabatic Flip-Flops and Sequential Circuits with Power-Gating Scheme

摘要：

This paper presents the implementations of adiabatic flip-flops and sequential circuits using single-phase power-clock with power-gating scheme. All circuits are realized by using the improved single-phase CAL (clocked adiabatic logic) technology. A power-gating scheme for the improved CAL circuits is used to reduce energy dissipation in sleep mode. All circuits are implemented using Chartered 0.35μm CMOS technology,and full-custom layouts are drawn.Based on the HSPICE simulations with post-layout extracted parasitic,the single-phase adiabatic sequential circuits with the power-gating scheme attain large energy savings over a wide range of frequencies,as compared with conventional CAL circuits and improved CAL circuits.

关键词： Adiabatic logic Single-phase flip-flop Power-gating Low-power design

作者: Haiyan Ni Jianping Hu

作者单位: Faculty of Information Science and Technology,Ningbo University,Ningbo City,Zhejiang 315211,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 879-882

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）