High Performance and Low Latency Mapping for Neural Network into Network on Chip Architecture

摘要：

Various hardware implementations of neural networks have been studied well in recent years.We have already proposed a hardware implementation method for neural network with a Network on Chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed,so that different mapping methods are needed every time and tedious or burdensome works are required.In this paper,we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.

关键词： Artificial Neural Network (ANN) Network on Chip (NoC) NoC architecture mapping method hardware implementation

作者: Yiping Dong Yang Wang Zhen Lin Takahiro Watanabe

作者单位: Graduate School of Information,Production and Systems,Waseda University,Japan

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 891-894

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）