A Data-flow Graph Generation Algorithm for a Coarse-grained Reconfigurable Processor

摘要：

In this paper,we present a C-to-DFG generation algorithm for coarse-grained reconfigurable processor in multimedia application feld. The algorithm exploits the operation parallelism available in the sequential code;maximizes parallelism by loop unrolling and scalar replacement.Loop unrolling increases the size of basic block and fully exposes the intrinsic data parallelism.Scalar replacement eliminates memory access instructions from the basic block under the prerequisite condition of keeping data dependency.For mapping kernels,the three parts of DFGs are corresponding to the three sub-components of reconfigurable unit. The experiments evaluating the degrees of parallelism on DFGs suggest 5.2x to 120.4x speedups on four kernels from common multimedia algorithms.

关键词： data-flow graph reconfigurable processor compilation

作者: Chao Yang Shouyi Yin Leibo Liu Shaojun Wei

作者单位: Tsinghua National Laboratory for Information Science and Technology,Institute of Microelectronics,Tsinghua University Beijing 100084,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 898-901

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）