A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation
This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture.Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real time lane departure warning system.
Vision Chip Safety Driving Assist Lane Detection Dual-Core Processing Element Array
Yuan-Jin Li WanCheng Zhang Nan-Jian Wu
State Key Laboratory for Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
917-920
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）