Power Analysis Resistant AES Crypto Engine Design and FPGA Implementation for a Network Security Co-processor

摘要：

In a high performance network security coprocessor,the low power masking technique is used to promote the power attack resistant level of the AES crypto engine.Based on the original AES module which shares one s-box when ciphering and decoding,in order to achieve higher security,the novel circuit design of masking is achieved by two ways respectively,one utilized sRAM,the other replicated some modules. Over 1000 different power curves are recorded and compared between the two masked engines and the original one respectively,and over 10000 curves are recorded to show the strength of the masking architecture. The design is verified to be feasible by FPGA.

关键词： Power Analysis Masking SRAM Replicated Structure

作者: Yingjie Ji Liji Wu Xiangmin Zhang Xiangyu Li

作者单位: Institute of Microelectronics of Tsinghua University,Beijing 100084,P.R China Institute of Mieroelectronics of Tsinghua University,Beijing 100084,P.R China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 933-936

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）