Architectural Integration of RSA Accelerator into MIPS Processor

摘要：

In the domain of information security, people are now prone to implement the cryptographiC algorithm through hardware.Usually,these algorithms are designed as coprocessors and a system integrator must use some kind of protocol to correctly use it. This paper presents a convenient way to integrate RSA-engine onto MIPS processor based system by making use of the CP2 extension of MIPS architecture. A concrete implementation of RSA is given, and a dedicated hardware architecture is presented to integrate the MIPS processor and RSA accelerator. Also,software issues are raised and sample codes are given.

关键词： RSA MIPS information security instruction eztention

作者: Shiting Lu Suiyu Zhang Yulong Zhang Jun Han Xiaoyang Zeng

作者单位: State-Key Lab of ASIC and System,Fudan University,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 948-951

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）