Integrated CMOS Amplifier with Offset Rejection Scheme for Sensor Application
This paper presents the compacted design of a low-offset and low-power CMOS amplifier aimed for sensor applications,using a continuous-time active DC offset rejection design technique.In this design a CMOS amplifier with active DC rejection scheme and a supply and temperature insensitive current reference were adopted to minimize the systematic offset. The circuit was designed in sMIC 0.18-μm 1P6M CMOS technology,with an active die area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV,the offset drift about 0.27 μV/℃ for temperature ranging from -30℃ to 100℃ and the total power dissipation consumed as low as 37.8/μW from a 1.8 V single supply. The proposed amplifier also achieved CMRR and PSRR more than 85 dB and 101 dB,respectively.It dedicated to monitor very low amplitude signals recording,such as biomedical signals.
CMOS amplifier low-offset and low-power DC offset rejection integrated sensor
Jinyong Zhang Bin Li Lei Wang
School of Electronic and Information Engineering South China University of Technology,Guangzhou,Chin School of Electronic and Information Engineering,South China University of Technology,Guangzhou,Chin Institute of Biomedical and Health Engineering,Shenzhen Institutes of Advanced Technology,Chinese Ac
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
959-962
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）