Design and FPGA Implementation of JAVA CARD Coprocessor for EMV Compatible IC Bankcard

摘要：

To meet the urgent need of transferring magnetic stripe bankcard to IC bankcard,a 16-bit low power JAVA CARD coprocessor for EMV compatible IC bankcard is designed and implemented by FPGA.in order to speed up the running of the JAVA CARD applets,a novel 5-stage pipelined JAVA CARD coprocessor is achieved with pure logic circuits, which carries out the execution of 88 instructions out of 134 defined in the JA VA CARD Virtual Machine specification 3.0 Classic Edition,while the remaining instructions are processed by the main 32-bit RISC processor. A pre-fetch instruction buffer and stack-top-register are used to ensure the fluency of the pipeline for accelerating the coprocessor. The design is verified to be feasible for the need of IC bankcard by FPGA and proved significantly faster than the regular software virtual machine,while remaining in a low power consumption level.

关键词： Bankeard JAVA CARD Coprocessor Pipeline

作者: Di WU Liji WU Xiangmin ZHANG

作者单位: Institute of Mieroelectronics,Tsinghua National Laboratory for Information Science and Technology,Ts Institute of Microelectronics,Tsinghua National Laboratory for Information Science and Technology,Ts

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 971-974

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）