An Multi-Rate LDPC DeCoder Based on ASIP for DMB-TH

摘要：

Based on ASIP (Application Specific Instruction Set Processor),this paper propose a decoder architecture for LDPC (Low Density Parity Check Codes) in the DMB-TH standard. The decoder use a five-stage pipeline,32-bit RISC processor and it can supports three different code rates (0.4,0.6 and 0.8) by only modifying the program.Based on XC4VLX150,at the max frequency of 126 MHz,the max throughput of the decoder can achieve 96Mps for 10 TDMP-decoding Iterations.Compared with other GPP and DSP implementations,this ASIP simplify the control logical and enhance the flexibility.

关键词： decoder multi-rate ASIP DMB-TH TDMP

作者: Xiaojun Zhang Yinghong Yian Jianming Cui Yuyin Xu Zongsheng Lai

作者单位: East China Normal University,Shanghai,China Fudan university,East China Normal University,Shanghai,China Shandong university of science and Technology,Taian,Shandong Province IMCS,East China Normal University,Shanghai,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 995-998

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）