Low-Complezity Architecture of RS Decoder for CMMB System

摘要：

Based on the Berlekamp-Massey algorithm,a low-complexity VLSI architecture of Reed-Solomon decoder for CMMB is presented in this paper. The proposed scheme has a folded systolic architecture,in which both error-locator and the error-evaluator can be computed in a single array of processors.With the folding property of the systoliC array architecture,the number of the multipliers and the adders are reduced drastically. The architecture chooses 8 as the folding factor,as a result,80% fewer multipliers and adders are used in the proposed architecture than in the RiBM architecture. The reduction in the number of multipliers and adders lead to smaller silicon area and lower power consumption. The proposed RS (240,224) decoder design is implemented and fabricated in HJTC 0.18μm 1P6M CMOS technology.

关键词： Reed-Solomon decoder low-complezity RiBM folded systolic architecture

作者: Kun Guo Yong Hei Shushan Qiao

作者单位: Institute of Microelectronics of Chinese Academy of Sciences,Beijing,100029,Peoples Republic of Chi Institute of Mieroelectronics of Chinese Academy of Sciences,Beijing,100029,Peoples Republic of Chi

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1003-1006

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）