A Cost efficient LDPC decoder for DVB-S2

摘要：

Based on the Min-Sum algorithm,this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2,which includes 11 kinds of code rates with a block size of 64800. Based on SM1C 0.13μm standard CMOS process,the LDPC decoder has an estimation area of 14mm2,a throughput of 135Mbps with a frequency of 105MHz and maximum iteration number of 30,which shows advantage over previous DVB-S2 LDPC decoders.

关键词： LDPC coeds DVB-S2 min-sum TDMP schedule

作者: Yan Ying Dan Bo Shuangqu Huang Bo Xiang Yun Chen Xiaoyang Zeng

作者单位: State Key Lab.of ASIC and System,Department of Microelectronics,Fudan University,shanghai,China State Key Lab.of ASIC and System,Department of Mieroelectronics,Fudan University,shanghai,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1007-1010

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）