The Gate-Bias Influence for ESD Characteristic of NMOS

摘要：

The positive and negative gate-bias effect on ESD robustness of NMOS devices are analyzed respectively in this paper. The influence of gate-bias have been simulated by ISE TCAD and discussed. The simulation results indicate that the triggering voltage fell from 10.46V to 7.8V with the negative gate bias changed from OV to-10V,and reduced from 10.46V to 5.92V with the positive gate bias changed from OV to 3V.Under appropriate gate bias,the ESD protection devices can obtain lower Vt1 and higher Vt2.It gives benefit of triggering the large-dimension MOS uniformly, which can improve ESD robustness directly.

关键词： ESD gate-bias effect NMOS TCAD

作者: Juan Liu Hang Fan Jianguo Li Lingli Jiang Bo Zhang

作者单位: State Key Laboratory of Electronic Thin and Integrated Device,University of Electronic of Electronic Science and Technology of China,Chengdu 610054,P.R.China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1047-1050

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）