The Size Optimize of DCVSPG Logic

摘要：

In this paper,a simple delay model for manual analysis of DCVSPG logic is built to evaluate the delay of the circuit. The delay obtained by the model is very close to that obtained by HSPICE Also the model can be used to optimize the size of NMOS transistors in DCVSPG logic under specific constraints. At last,the technique how to use this model is displayed.

关键词： DCVSPG logic RC model Elmore delay

作者: Yuanbin Xie Weitao Pan Peijun Ma Yue Hao

作者单位: Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xian 710071,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1051-1054

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）