A Sample/Hold Circuit for 80MSPS 14-bit A/D Converter
In this paper,a sample/hold circuit for switched capacitor structure in 0.um CMOS process technology is described. The sample/hold circuit is used for-bit pipelined a/D converter with a conversion rate up to OMSPS.In the circuit,the differential unity gain structure is employed. The impact of channel in ected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted,so desired gain and bandwidth of the circuit are obtained.By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of is-OdB at OMSPS with input signal of 2 pp. As a result,the D L is 0./-0.LSB,the I L is./-.LSB,the S Ris 0.2dB,and the SFDR is .dB.
A D converter sample hold switched capacitor circuit 0.3 um CMOS linearity SNR
iao Kunguang Wang Yuxing u Minyuan Zhu Chan
Sichuan Institute of Solid-States,CECT,Chongqing 400060,P.R.China National Laboratory of Analog Integrated Circuits,Chongqing 400060,P.R.China
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
1093-1096
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）