A Low Power Self-Sampling IF FSK Receiver

摘要：

A low power IF FSK receiver is presented. The receiver consists of one limiter and one self-sampling FSK demodulator. The limiter uses the replica biasing circuit technique to avoid the effects of P T variation. to minimize the power consumption,a low supply CDL is adopted,and the reference cloc frequency of DLL is also decreased. The receiver has been implemented in 0.um CMOS process and the simulated results show that the receiver could accurately demodulate the signal with a data rate of 2Mbps and a IF carrier frequency of OMHz and achieves a IF carrier frequency offset tolerance of MHz. The power consumption of the IF FSK receiver is 2.mW. The demodulator part consumes only 0.mW.

关键词： fre uency shift keying (FS) demodulator CMOS integrated circuits Low IF receiver

作者: Yang u Baoyong Chi Zhihua Wang

作者单位: Institute of Microelectronics,Tsinghua University,Beijing 100084,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1113-1116

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）