A Parallel-Amplification Parallel-Summation Logarithmic Amplifier for UHF RFID Reader

摘要：

This paper describes a four gain paths parallel-amplification parallel-summation logarithmiC amplifier (PPLA).It is used in the UHF RFID Reader as a part of the ASK demodulating system to compress the high dynamic range input signal.Compared with the successive detection logarithmic amplifier (SDLA),the PPLA has wider bandwidth,and is easier to meet requirement of the system stability. The presented PPLA is implemented in IBM 0. 18um CMOS technology with dynamic range of 70dB,bandwidth of IMHz,and power dissipation of 19 mW.

关键词： RFID PPLA RSSI

作者: Zhang Yong Chen Lei Zhang Xiao-jun Lai Zong-sheng

作者单位: Institute of Mieroelectronics Circuit & System,department of Mieroelectronics and Solid-Stare Electr IMCS in East China Normal University,Shanghai,China Shandong University of Science and Technology IMCS in East China Normal University,Shanghai,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1121-1124

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）