Design of a 2.5Gbps Clock-Data Recovery circuit in 0.18um standard CMOS process

摘要：

A 2.5Gbps Clock-Data Recovery (CDR) circuit is designed in 0.18um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.SGHz by SONET OC-48 while the CMU loop runs at 625MHz. The power consumption is 25m W. The jitter bandwidth is 5.6MHz. The peaking is 2.67dB. The VCO gain is 163MHz/V with a tuning range of 390MHz. The output data and clock amplitude is 500m V SEPP (singleended peak to peak). Random Jitter is 0.1mUI rms and the output data ISI is 10mUI.

关键词： CDR CMOS PLL CMU high-speed

作者: Chen Yueyang Zhong Shunan Dang Hua

作者单位: School of Information and Electronics,Beijing Institute of Technology,Beijing,10081 China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1153-1156

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）