A Novel Fast-Settling ADPLL Architecture with Frequency Tuning Word Presetting and Calibration

摘要：

A time domain behavior modeling for fastsettling all digital phase-locked-loop (ADPLL) is proposed.By using the frequency presetting and adaptive bandwidth algorithm,this ADPLL can lock within 2μs according to the simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling.

关键词： all-digital phase-locked loop (ADPLL) fastsettling adaptive bandwidth behavior model

作者: Weicheng Zhang Xuan Dai Jing Jin Jianjun Zhou

作者单位: Center for Analog/RF IC(CARFIC),School of Microelectronic,Shanghai Jiaotong University,Shanghai,2002 chief of Center for Analog/RF IC(CARFIC),School of Microelectronic,Shanghai Jiaotong University,Shan

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1161-1164

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）