Design of 16-bit 400MSPS Current Steering D/A Converter

摘要：

In this study,design of a 16-bit,400MSPS high speed high-resolution current steering D/A converter is described.With pipelined thermometer decoding,multi-stage synchronous latch,current-source matching array design, two-stage active cascade design,and current switch nonlinear capacitor bootstrapping compensation technologies,DAC dynamic performances at high frequency are improved. The DAC uses the design in 0.25um CMOS process technology.Its die size is 4.84 mm×4.9mm.High-frequency broadband sFDR>63dBc@,Fout=(331/1024)×400 MHz & Fsamle =400MHz;

关键词： Current-Steering DAC matching dynamic linearity active cascode SFDR

作者: Fu Dongbing Zhu Dongmei Zhou Shutao Li Kaicheng

作者单位: National Labs of Analog Integrated Circuits and Sichuan Institute of Solid-state Circuits,Nanan,Cho Sichuan Institute of Solid-state Circuits,Nanan,Chongqing 400060 China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1189-1192

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）