Full Coverage Location of Logic Resource Faults in A SOC Co-Verification Technology Based FPGA Functional Test Environment

摘要：

Full coverage location of logic resource faults is vital for FPGA design and fabrication,rather than only detecting whether there are faults or not. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware,SOC co-verification technology based in-house FPGA functional test environment embedded with an in-house computerized tool,ConPlacement,can locate logic resources automatically,exhaustively and repeatedly. The approach to implement full coverage location of configurable logic block (CLB) faults by the FPGA functional test environment is presented in the paper.Experimental results of XC4010E demonstrate that full coverage location of logic resource faults as well as multi-faults position can be realized.

关键词： FPGA full coverage location SOC co-verification logic resource fault

作者: Y.B.Liao P.Li A.W.Ruan W.Li W.C.Li

作者单位: State Key Laboratory of Electronic Films and Integrated Devices,University of Electronic Science and Technology of China,Chengdu,610054,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1228-1231

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）