Design of SoC Verification Platform Based on VMM Methodology

摘要：

A VMM-based verification platform has been implemented and applied to Yak SoC in this paper. The whole verification environment uses the SystemVerilog language, and the simulation tool adopted is Synopsys VCS-MX200606. The verification IP and SystemVerilog assertions help to heighten the performance of the platform. The verification results indicate that design errors of timing and anti-protocols have been exactly checked out with 100% verification coverage,The proposed platform,possessing fine configurability,flexibility and high performance,can be reused in similar verifications of other design.

关键词： VMM verification IP assertion coverage

作者: Lu Kong Wu-Chen Wu Yong He Ming He Zhong-Hua Zhou

作者单位: VLSI & system Lab,Beijing University of Technology,Beijing 100124 China VLSI and System Lab.,Beijing University of technology,Beijing 100124 China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1272-1275

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）