Transistor Permutation for Better Transistor Chaining

摘要：

Custom layout design style remains to be an ef fective way of improving and differentiating the performance of integrated circuits.In this paper,we revisit the classic problem of transistor chaining,a key step in transistor level layout generation and report a systematic method for permutating transistors in a circuit topology such that without altering its logic function,the chance of finding transistor chains with minimum number of diffusion breaks is increased. The results on nontrivial circuits show that our algorithm can consistently outperform the best reported results in the literature.

关键词： Transistor chaining transistor permutation bipartite graph abutment upper bound

作者: Xun Chen Jianwen Zhu

作者单位: PDL,School of Computer,National University of Defence Technology,410073,ChangSha,China Electrical and Computer Engineering,University of Toronto,ON,M5S 3G4,Canada

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 1276-1279

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）