A Simulated Annealing Based Technology Mapping Method for Sequential Circuits

摘要：

Due to the rapid growth of traffic in Internet, backbone links of 40 gigabits per second are commonly deployed. To handle high traffic rates, the backbone routers must be able to forward millions of packets per second on each of their ports. Pipelined design can effectively support high speed packets processing. Technology mapping method for sequential circuits in FPGA is playing vital role to pipelined design. This paper presents a simulated annealing based technology mapping method for sequential circuits. The proposed method not only guarantees minimal clock period for pipeline level, but also saves FPGA resources.

关键词： pipeline sequential technology mapping simulated annealing retiming

作者: Peng Li Julong Lan Dan Li Qiang Liu

作者单位: National Digital Switching System Engineering & Technological Research Center Zhengzhou 450002,China

会议类型: 国际会议

会议名称: 2009 First International Conference on Future Information Networks(第一届未来信息网络国际会议)

会议地点: 北京

会议语种:英文

页码: 303-307

在线出版日期: 2009-10-14（万方平台首次上网日期，不代表论文的发表时间）