Fast Placement for Large-scale Hierarchical FPGAs

摘要：

In this paper, we propose a fast placer for FPGA placement on a new commercial hierarchical FPGA device. The novelty of this research lies in the application of a multilevel V-shape optimization flow including an architecture related cluster process and a constructive placement. The new placer can handle large-scale FPGA placement problem quickly. Experimental results show that the proposed placer can further reduced the wirelength average 28.3% compared with simulated annealing based tool while achieving near 5X speedup in runtime for the five largest MCNC benchmarks.

作者: Hui Dai Qiang Zhou Yici Cai Jinian Bian Xianlong Hong

作者单位: EDA laboratory, Dept. of Computer Sci. & Tech. Tsinghua University Beijing 100084, P. R. China

会议类型: 国际会议

会议名称: 11th IEEE International Conference on Computer-Aided Design and Computer Graphics(第11届IEEE国际计算机辅助设计与图形学学术会议 IEEE CAD/GRAPHICS 2009)

会议地点: 黄山

会议语种:英文

页码: 190-194

在线出版日期: 2009-08-19（万方平台首次上网日期，不代表论文的发表时间）