An Approach to Synthesis Delay Semantics in VHDL
The detailed timing information obtained from design iteration can only be added into synthesis process manually. A new strategy for automatic synthesis of backing marked timing information is presented in this paper. As the carrier of backing marked timing information, the delay statements in VHDL is synthesized in scheduling process. And a new scheduling algorithm is presented in this paper. The delay statements are considered to be delay time constraints by the algorithm. Scheduling data structure: DTC_DFG(Delay Time Constrained Data Flow Graph) is constructed and scheduled. A heuristic method is presented in this paper for the scheduling algorithm to jump out local optimization and reach global optimization under polynomial timing complexity. Experimental results are also presented in this paper. With the synthesis of delay statements, the backing marked timing information can be synthesized automatically, and the behavioral timing in design source can be synthesized directly, thus the timing consistency between synthesis result and simulation result can be improved. The delay statements then can be a convenient means to set timing constraints, thus the manual interruption in synthesis process can be decreased; the design efficiency can be improved greatly.
Cheng lixin Bian jinian Liu yunyun
Computer Science and Technology College, Harbin Engineering University, Harbin, China Department of Computer Science and Technology, Tsinghua University, Beijing, China Network Information Center, Harbin Engineering University, Harbin, China
国际会议
黄山
英文
492-496
2009-08-19（万方平台首次上网日期，不代表论文的发表时间）