The Design of Clock Distribution in the Parallel/interleaved Sampling System

摘要：

The paper introduced the mathematical model in both time and frequency domain of parallel/interleaved sampling system,the total gain error,phase shift error,aperture jitter error of multi-channel sampling scheme are all involved. The critical layout techniques of a hi-speed and hi-resolution analog-todigital conversion circuit are also provided. At last,a 4-channel interleaved sampling clock circuit with the jitter level of sub-picosecond is given,whose phase noise and jitter test results are also shown.

关键词： parallel/interleaved AID converter clock distribution jitter phase noise.

作者: Cao Peng Wang Mingfei Qi Wei Fei Yuanchun Tian Haiyan Meng Fanjun

作者单位: School of Information and Mechanical Engineering,Beijing Institute of Graphic communication,Beijing School of Information and Electronics,Beijing Institute of Technology,Beijing 108100 China

会议类型: 国际会议

会议名称: 2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)

会议地点: 北京

会议语种:英文

页码: 543-546

在线出版日期: 2009-08-16（万方平台首次上网日期，不代表论文的发表时间）