Architecture of Out of Order TURBO51 Embedded Microprocessor

摘要：

In this paper,it is firstly give the background and the considerations to follow this technological roadmap of design the TURBO5I. It then introduces the architecture design of instruction out of order pipeline,includes the branch prediction,dynamical execution and memory management. The various test patterns in running real applications indicates that TURBO51 has one-time successful taped out and under the same work clock frequency,it outperforms over 20 times faster than its traditional counterpart. However,owing to no implementation of a full DataCache and the three-layer-memory-hierarchy,the performance over 100MHz is supposed to be hampered and automatic test vector generation in verification needs further enhancement.

关键词： 8051 embedded microprocessor architecture design dynamical ezecution branch prediction serial flash

作者: Xiaofei Wu

作者单位: Weststar Chips,Chengdu,China

会议类型: 国际会议

会议名称: 2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)

会议地点: 北京

会议语种:英文

页码: 1284-1289

在线出版日期: 2009-08-16（万方平台首次上网日期，不代表论文的发表时间）