A Built-in Self-test Design with Low Power Consumption Based on Genetic Algorithm

摘要：

A low peak power consumption built-in self-test (BIST) design based on genetic algorithm (GA),which is denoted by GAITPG,has been proposed in our previous study. This paper presents an improved performance of GAITPG,which also aims at the reduction of the changes between successive test patterns. (m-I) vectors were inserted between two successive n-bit pseudorandom test patterns generated by the original linear feedback shifted register (LFSR),while m and the element of groups were optimized by GA. Experimental results based on ISC aS85 benchmark circuits show that the test pattern generator (TPG) with low power consumption proposed in this paper is efficient,without losing stuck-at fault coverage. Also,a comparison of reduction of power consumption between GAITPG and other scheme (such as inserted TPG (ITPG)) was reported.

关键词： low power consumption design GA BIST TPG LFSR weighted switching activity (WSA)

作者: Enmin Tan Li Wang

作者单位: School of Electronic Engineering,Guilin University of Electronic Technology,Guilin,541004,China

会议类型: 国际会议

会议名称: 2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)

会议地点: 北京

会议语种:英文

页码: 1603-1606

在线出版日期: 2009-08-16（万方平台首次上网日期，不代表论文的发表时间）