Design and Implementation of an Improved 3G Turbo Codes Interleaver for 3GPP System

摘要：

Interleaver is important part in turbo encoder and decoder. The special third generation (3G) interleaver had been included in the released 3rd Generation Partnership Project (3GPP) specifica- tion and standard. The complex interleaver algorithm is described first. Then Verilog HDL Implementation of an improved interleaver is presented. By using RAM block, interleaver algorithm is transformed to address controlling of RAM reading and writing in order to simplify interleave process. It shows that encoding and decoding delay can be shorted effectively. The design was proved correctly by experiment and had been made use of in turbo encoder and decoder as a module.

关键词： turbo codes 3GPP interleaver IP core

作者: Xianhua Yin Jianqiang Liu

作者单位: School of Electronic Engineering,Guilin University of Electronic Technology,Guilin,China Shenzhen Huawei technology Ltd.,Shenzhen,China

会议类型: 国际会议

会议名称: 2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)

会议地点: 北京

会议语种:英文

页码: 2447-2449

在线出版日期: 2009-08-16（万方平台首次上网日期，不代表论文的发表时间）