Boundary Scan with Parallel Test Access Mechanism

摘要：

Along with the more complicated integrated circuit and emergence of IP based systems on a chip (SoC), new challenges are encountered in the designing for testability (DFT). The test power dissipation is one of the critical factors which should be considered carefully when designing the SoC for testability. In this paper, a parallel test access mechanism using boundary scan technique is proposed with its test controller. The test action mechanism (JAM) and the controller can be selected flexible for the test cost and the power dissipation.

关键词： Designing for testability (DFT) boundary scan technique Joint Test Action Group (JTAG) test power dissipation.

作者: Han Ke Deng Zhongliang Huang Jianming

作者单位: School of Electronic Engineering,Beijing University of Posts and Telecommunications Beijing 100876,China

会议类型: 国际会议

会议名称: 2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)

会议地点: 北京

会议语种:英文

页码: 3298-3301

在线出版日期: 2009-08-16（万方平台首次上网日期，不代表论文的发表时间）