Phase Noise Analysis and Design of CMOS Differential Ring VCO
A complete six-order CMOS differential ring voltagecontrolled oscillator (VCO) is designed with a 0.35μm CMOS process in this paper. The circuit has been successfully applied in a CPPLL of a high-speed high-resolution DAC, and has been successfully taped out and passed the test. The relative factors that influence the VCO phase noise are analyzed comprehensively to instruct the circuit design. The designed differential ring oscillator includes the VCO unit circuit, the bias circuit for the tail current source, the start-up circuit, and the wave shaping circuit. The oscillation frequency of the designed VCO ranges from 96MHz to 400MHz. An improved VCO unit circuit was adopted to reduce the process influence and the coupling between the output and the ground, as well as to lower the phase noise by connecting a sub-pF magnitude capacitance to the output terminal. Moreover, the start-up circuit is designed to ensure that the VCO could start to oscillate quickly, and the optimal layout is designed to lower the influence of the noise. The circuit is simulated using 0.35μm CMOS process, the simulation results illustrate that the K(vco) exhibits an ideal linearity with a value of 467MHz/V and the phase noise has been lowered effectively with a value of -135dBc/Hz@1MHz in the typical operation condition. The test results show that the designed VCO could work properly and the CPPLL could be locked quickly. The designed VCO circuit could be applied in the electronic measurement equipments, providing a controllable and stable frequency signal for the system.
CMOS phase noise differential ring oscillator VCO.
Honghui Deng Yongsheng Yin Gaoming Du
Institute of VLSI design,Hefei University of Technology Tunxi Road 193,230009 Hefei(Anhui),China
国际会议
2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)
北京
英文
3959-3964
2009-08-16（万方平台首次上网日期，不代表论文的发表时间）