Research on Metastability based on FPGA

摘要：

Multi-clock is commonly used in complex systems. So if synchronous signals in one clock domain are transferred to another clock domain, they will become asynchronous signals. Asynchronous signals will cause metastable state, which will lead to unpredictable results. How metastabilities led to errors in a system is described first. Then a simulation of RS flip flop using pspice is to show the detail procedure of metastability. To demonstrate how often metastabilities will happen, a FPGA based experimentation is realized by changing the internal layout of flip flop manually, which changes the propagation delay between them.

关键词： metastability FPGA multi-clock domain.

作者: Jie Wu Yichao Ma Jie Zhang Yang Kong Hongzhi Song Xiaoquan Han

作者单位: Department of Modern Physics,University of Science and Technology of China,Jin Zhai Road 96,230026,H Bureau of Geophysical Prospecting,072751,Zhuozhou,Hebei,China

会议类型: 国际会议

会议名称: 2009 9th International Conference on Electronic Measurement & Instruments(第九届电子测量与仪器国际会议 ICEMI2009)

会议地点: 北京

会议语种:英文

页码: 3969-3973

在线出版日期: 2009-08-16（万方平台首次上网日期，不代表论文的发表时间）