LOGIC EQUIVALENCE CHECK IN SOC DESIGN: SOLUTION AND ISSUES

摘要：

When the design becomes complex and costly in sub-micron SOC chips, formal verification –logic equivalence check becomes increasingly important to meet the design challenging and schedule. This paper shows its method and application in one reconfigurable system-on-chip’s physical design and full chip integration phase. We described the key learning from this project.

关键词： Formal verification Logic equivalence check Reconfigurable system SOC VLSI chip design

作者: Qing K. Zhu

作者单位: Chameleon Systems Inc, 7848 Pineville Circle, Castro Valley, CA 94552, USA

会议类型: 国际会议

会议名称: China-Ireland International Conference on Information and Communications Technologies 2008(2008 中国-爱尔兰信息与通信技术国际会议 CIICT 2008)

会议地点: 北京

会议语种:英文

页码: 1-4

在线出版日期: 2008-09-26（万方平台首次上网日期，不代表论文的发表时间）