FREQUENCY SCALING FOR MULTIDIMENSIONAL PACKET CLASSIFIERS
With an ever growing number of packet processing applications and an increasing volume of internet traffic the need to design networking equipment for both low power and high throughput is as important as ever. In this paper we present a scheme for frequency scaling, which adjusts the clock frequency to a packet classification hardware accelerator so that it matches the incoming traffic volume to a router’s line card. This is done by buffering the incoming packets and then using the number of packets buffered as a threshold to run the packet classification hardware accelerator at the lowest clock frequency that can service the buffer without dropping packets. To do this we developed a scheme which keeps the number of clock frequency switches to a minimum. Simulation results show that savings of up to 19% can be made when a packet classification hardware accelerator with frequency scaling is implemented on a Startix 3 FPGA, and up to 57% power savings can be achieved when implemented on Cyclone 3 FPGA.
Low Power Frequency Scaling Packet Classification
Alan Kennedy Xiaojun Wang Zhen Liu Bin Liu
School of Electronic Engineering, Dublin City University, Dublin 9, Ireland Department of Computer Science and Technology, Tsinghua University, Beijing 100084 China
国际会议
北京
英文
1-5
2008-09-26（万方平台首次上网日期，不代表论文的发表时间）