Development of A Flezible Hardware Core for Genetic Algorithm

摘要：

A hardware design for genetic algorithm (GA) can implement only one specific cost function of a problem at a time. Actually, different GA applications require different GA hardware architecture. The development of a flexible verylarge-scale integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, we has develop on a random number generator (RNG), crossover, and mutation based on flexibility structure. This structure can dynamically perform to the 3 types chromosome encoding: binary encoding, real-value encoding, and integer encoding. The overall structures has been designed and synthesized by VHDL (VHSIC hardware description language), simulation by ModelSim program, and then implemented on FPGAs (Field programmable gate arrays). This hardware architecture that our design work very well flexible for the 3 groups problem examples: combinatorial optimization problems, function optimal problems, and part planning optimization problems.

关键词： Genetic Algorithm(GA) Chromosome encoding ModelSim VHSIC hardware description language(VHDL) Field programmable gate arrays(FPGAs).

作者: Jumrern Pimery Pinit Kumhom

作者单位: Department of Electronic and Telecommunication Engineering King Mongkuts University of Technology Thonburi 126 Pracha-utid Road,Bangmod,Tungkru,Bangkok,10140 Thailand

会议类型: 国际会议

会议名称: 2009 IEEE International Conference on Intelligent Computing and Intelligent Systems(2009 IEEE 智能计算与智能系统国际会议)

会议地点: 上海

会议语种:英文

页码: 867-870

在线出版日期: 2009-11-20（万方平台首次上网日期，不代表论文的发表时间）