A Multi-Modulus Programmable Frequency Divider With 33.3％ to 66.7％ Duty Cycle Output Signal

摘要：

A multi-modulus programmable frequency divider architecture with 333％ to 66.7％ duty cycle output signal is presented. Key circuits of the architecture are 2/3 divider cells, which share the same logic and almost same circuit cells. This architecture can divide the input clock frequency by 22 to 2n+1 -1 with unit step increment, where n is the number of 2/3 divider cells; and 33.3％ to 66.7％ duty cycle output signal greatly improve output load driver capable.

关键词： multi-modulus programmable divider 2/3 divider duty cycle

作者: Fei Cai Hong-Lin Chen Hua-Bin Zhang Yong-Ping Wang

作者单位: Radio Frequency IC Division Runxin Information and Technology Co.,Ltd.Guangzhou,China School of electronic and information engineering South China University of Technology Guangzhou,Chin Strategic Development Division Runxin Information and Technology Co.,Ltd.Guangzhou,China

会议类型: 国际会议

会议名称: 2009 IEEE International Conference on Intelligent Computing and Intelligent Systems(2009 IEEE 智能计算与智能系统国际会议)

会议地点: 上海

会议语种:英文

页码: 2045-2047

在线出版日期: 2009-11-20（万方平台首次上网日期，不代表论文的发表时间）