Implementation of Simple SNORT Processor for Efficient Intrusion Detection Systems
In this paper, a method is proposed for hardware implementation of basic instructions of SNORT software for using in hardware accelerator systems relating to Network Intrusion Detection (NID). The design is implemented in Verilog hardware description language. The design is synthesized both in FPGA on Virtex5 and ASIC (with CMOS Technology 90nm and 65nm). Initial results of hardware description simulation agree with those of SNORT. Similarity between these two results shows that the proposed hardware infrastructure can be exploited as a hardware accelerator in different applications of Intrusion Detection (ID) within networks where needs high processing rate for multi Gb/s data rates. The ASIC synthesis results indicate that the proposed hardware can process payload section of a TCP/IP stream with the rate of 1 Gb/s and 2 Gb/s in TSMC 90nm and TSMC 65nm respectively.
network intrusion detection systems hardware accelerators snort hardware description languges FPGA ASIC
Ehsan Azimi M.B.Ghaznavi-Ghoushchi Amir Masoud Rahmani
Dept.of CE.School of Engineering Islamic Azad University,Science and Research Branch Tehran,Iran Dept.of EE.School of Engineering Shahed University Tehran,Iran ghaznavi AT shahed.ac.ir
国际会议
上海
英文
2348-2352
2009-11-20（万方平台首次上网日期，不代表论文的发表时间）