A LDPC Decoder with All Single Port Memories

摘要：

this paper proposes one LDPC decoder with all single port memories to lower requirements of logic and interconnection and save hardware cost. Considering the lower read-write speed of single port memories than that of dual port memories, the decoder needs to reduce computation complex and shorten the critical path delay so as to get high throughput. To get the purpose, the LDPC decoder uses TDMP algorithm and normalized MS algorithm to reduce computation complex, uses reusable and configurable CVPU to realize single cycle pipeline variable and check node updating calculation, uses optimized shuffle network to shorten the path delay, and uses memories dominated controller to avoid the read and write conflict of memories. The implementation results show for once iteration process the throughputs are about 890Mbps, 847Mbps, and 863Mbps for rate 0.4,0.6, and 0.8 respectively.

关键词： LDPC TDMP MS single port memory

作者: Ying-Hong Tian Xiao-Jun Zhang Zong-Sheng Lai

作者单位: East China Normal University,Shanghai,China

会议类型: 国际会议

会议名称: 2009 IEEE International Conference on Intelligent Computing and Intelligent Systems(2009 IEEE 智能计算与智能系统国际会议)

会议地点: 上海

会议语种:英文

页码: 2362-2365

在线出版日期: 2009-11-20（万方平台首次上网日期，不代表论文的发表时间）