An ASIP Encoder for Quasi-Cyclic LDPC Codes

摘要：

This paper proposes a LDPC (Low Density Parity Cheek Codes) encoder architecture for DMB-TII based on ASIP (Application Specific Instruction Set Processor). The encoding algorithm is first analyzed and optimized for the ASIP encode, And then the special instruction sets are extracted according to the optimized algorithm. The ASIP architecture uses main processor and coprocessor to get high throughput. This ASIP encoder can support three different code rates (0.4, 0.6 and 0.8) just by different programs and thus is more flexible than other ASIC implementa-tions. Based on XC2V6000, at the max frequency of 117MHz, the max throughput of the encoder can deliver 187MI>ps, 206Mbps and 232Mbps for 0.4,0.6 and 0.8 code rates, respectively.

关键词： encoder ASIP DMB-TH LDPC

作者: Xiaojun Zhang Yinghong Tian Jianming Cui Yanni Xu Zongsheng Lai

作者单位: IMCS,East China Normal University,Shanghai,200062,China IMCS,East China Normal University,Shanghai,200062,China;Shandong University of Science and Technolog Shandong University of Science and Technology,Taian,271019,China

会议类型: 国际会议

会议名称: 2009 IEEE International Conference on Intelligent Computing and Intelligent Systems(2009 IEEE 智能计算与智能系统国际会议)

会议地点: 上海

会议语种:英文

页码: 2400-2403

在线出版日期: 2009-11-20（万方平台首次上网日期，不代表论文的发表时间）